A 16-BIT HIGH-SPEED MULTIPLIER DESIGN BASED ON KARATSUBA ALGORITHM AND URDHVA-TIRYAGBHYAM THEOREM USING MODIFIED GDI CELLS FOR LOW POWER AND AREA CONSTRAINTS

Nelson, Bobby and Tiwari, Ravi (2017) A 16-BIT HIGH-SPEED MULTIPLIER DESIGN BASED ON KARATSUBA ALGORITHM AND URDHVA-TIRYAGBHYAM THEOREM USING MODIFIED GDI CELLS FOR LOW POWER AND AREA CONSTRAINTS. ICTACT Journal on Microelectronics, 3 (2). pp. 398-403. ISSN 23951672

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Official URL: https://doi.org/10.21917/ijme.2017.0071

Abstract

The paper entails the design of a 16-bit multiplier with the combined application of Karatsuba algorithm and the Urdhva- Tiryagbhyam (UT) theorem and the implementation of the multiplier architecture in Modified-Gate-Diffusion-Input (Mod-GDI) cells for improving the area and power constraints in the proposed novel hybrid multiplier.

Item Type:	Article
Subjects:	Asian STM > Multidisciplinary
Depositing User:	Managing Editor
Date Deposited:	11 Jul 2023 03:56
Last Modified:	02 Oct 2023 12:36
URI:	http://journal.send2sub.com/id/eprint/1895

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